Communication Time Estimation in High Level Synthesis
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Date
2013
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Communication Time Estimation in High Level Synthesis
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Authors
Pilászy, György
Rácz, György
Arató, Péter
Rácz, György
Arató, Péter
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Publisher
Budapest University of Technology and Economics
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folyóiratcikk
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Open access
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2064-5260
2064-5279
2064-5279
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4
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57
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Periodica Polytechnica - Electrical Engineering and Computer Science
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Postprint
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99
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communication time estimation
HLS
CAD
microcontroller
multiprocessing
embedded systems
serial communication interfaces
HLS
CAD
microcontroller
multiprocessing
embedded systems
serial communication interfaces
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Tudományos cikk
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Journal Title
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Volume Title
Publisher
Budapest University of Technology and Economics
Abstract
The high level synthesis (HLS) tools may result in a multiprocessing structure, where the time demand of the interchip data transfer (briefly the communication) between the processing units (hardware or software) is determined exactly only after the task-allocation. However, a realistic preliminary estimation of the communication time would help to shape the scheduling and the allocation procedures just for attempting to minimize the communication times in the final structure. Compared to the task-execution times of the processing units, especially significant communication times are required by the serial communication interfaces which are frequently used in microcontroller systems. This paper presents an estimation method by analysing four well-known serial communication interfaces (SPI, CAN, I2C, UART).