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Reachability Analysis of Petri-nets by FPGA Based Accelerators 

Csertán Gy; Majzik, István; Pataricza, András; Allmaier S C ([s. n.], 1998)
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Automatic Verification of a Behavioural Subset of UML Statechart Diagrams Using the SPIN Model-checker 

Latella D; Majzik, István; Massink M (1999)
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Hierarchical Checking of Multiprocessors Using Watchdog Processors 

Majzik, István; Pataricza, András; Cin M Dal; Hohl W; Hönig J; Sieh V (Springer, 1994)
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Towards a Formal Operational Semantics of UML Statechart Diagrams 

Latella D; Majzik, István; Massink M (Kluwer Academic Publishers, 1999)
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Reachability and Timing Analysis in Data Flow Networks: A Case Study 

Antal B; Bondavalli A; Csertán Gy; Majzik, István; Simoncini L (IEEE Computer Society Press, 1996)
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Hardware Accelerators for Petri-net Analysis 

Csertán Gy; Majzik, István; Pataricza, András; Allmaier S C; Hohl W (Univ. Wien, 1998)
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A High-Speed Watchdog Processor for Multitasking Systems 

Majzik, István; Pataricza, András; Hohl W; Hönig J; Sieh V (Híradástechnikai Tudományos Egyesület, 1994)
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Automatic Dependability Modeling of Systems Described in UML 

Majzik, István; Bondavalli A (IEEE Computer Society Press, 1998)
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Formal Verification of Fault Tolerance Techniques in UML 

Majzik, István; Jávorszky J (Czech Technical University in Prague, 1999)
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Concurrent Error Detection of Program Execution Based on Statechart Specification 

Majzik, István; Jávorszky J; Pataricza, András; Selényi, Endre (Österreichische Computer Gesellschaft (ÖCG), 1999)

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Majzik, István (10)
Pataricza, András (5)Csertán Gy (3)Hohl W (3)Allmaier S C (2)Bondavalli A (2)Hönig J (2)Jávorszky J (2)Latella D (2)Massink M (2)... View MoreDate Issued1999 (4)1998 (3)1994 (2)1996 (1)Has File(s)
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